The present invention relates to a circuit configuration of a high speed digital signal processor achieving a realtime operation. The processor is applicable primarily to such fields as a video communication, high-definition digital television, and video signal processing.
Details concerning a digital signal processor have been described, for example, on pages 567 to 607 of the "LSI Handbook" published on Nov. 30, 1984 from OHM-Sha Ltd.
A digital signal processor is generally defined as a device in which digitized audio or video signals are processed or transformed by digital arithmetic circuits.
The digital operations performed by the digital signal processor include, for example, filtering, equalizing, noise reduction, echo cancellation, modulation, Fourier transformation, extraction of characteristic parameters of the signal, prediction of the signal, and emphasis of the video signal.
A signal outputted from the digital signal processor is restored through a digital-to-analog conversion to an analog signal, which is then fed to a low-pass filter to obtain a final output signal.
In 1980s, large scale integration (LSI) technology has been developed and there has been proposed application of specific LSIs in which the basic components of the digital signal processing, such as adders, multipliers, and unit delay registers, are arranged according to the signal processing flow of the specific application. Since the circuit size of the application specific to the custom LSI can be minimized, this is the most cost effective way when the LSIs are put to the mass production.
On the other hand, there has been proposed in late 1980s an LSI of a digital signal processor (to be referred to as DSP herebelow) which is controlled by a stored program. Since the algorithm of the signal processing is programmed using micro-instructions of the LSI such that the micro-instructions are read out from a memory so as to accomplish the algorithm, the LSI possesses a general-purpose characteristic. Various signal processing can be performed by programming this general-purpose DSP.
Incidentally, for a video signal compression in video communication, an orthogonal transformation, particularly, a discrete cosine transformation has been regarded as a potential candidate. A transformation equation is represented as follows, where {x.sub.k } and {y.sub.k } are inputs and outputs, respectively; and N stands for a block size of the data to be transformed. ##EQU1##
The 8th order transformation (N=8) of equation (1) can be expressed in a matrix notation as shown in equation (2). Taking the periodic characteristic of the trigonometric functions into consideration, there appear only 15 kinds of coefficients, namely; C.sub.1 to C.sub.15 to be multiplied by the inputs {x.sub.k }. ##EQU2##
Direct circuit implementation of equation (3) is shown in FIG. 2. This includes 8.times.8=64 multipliers 10 and 8.times.7=56 adders 11, if each of the adders allow only an addition of two inputs. In this situation, heretofore, as described in pages 23 to 30 of the Technical Review of the Institute of Electronic and Communication Engineers of Japan, IE85-4, 1985, the formula (3) is mathematically transformed so as to adopt a computation algorithm of FIG. 3. As a result, the numbers of the multipliers 30 and adders 31 are reduced to 11 and 29, respectively.
Incidentally, due to a recent advance in digital signal processors, it becomes possible to implement the algorithm shown in FIG. 3 using only a pair of elements comprising an adder and a multiplier. Here an adder and a multiplier are used in a time-shared fashion and the signal flow is controlled by a stored program.
FIG. 4 shows a digital signal processor (DSP) which develops a relatively high-speed operation and which includes a 4-port memory 12 and two data buses. This system has been discussed by the present inventors before the filing of this application. Table 1 shows a program which processes the algorithm of FIG. 3 by use of the processor. However, since the signal flow of this algorithm is irregular, high-speed processing techniques, such as a pipeline processing, are difficult. Therefore 29 steps are required for the data calculation alone. For the input/output operations of the data memory 12, eight steps are required even if the multiport operation of the memory 12 is taken into consideration. As a result, 29+8=37 steps are to be executed for a complete data processing. In addition, during the data calculation, the input/output operations are stopped. Therefore, the operation to match the input and output rates, which is achieved in the case of pipeline processing, cannot be realized. That is, a processing period of time of 37 steps is necessary. The machine cycle (the processing time for one step) of a processor having a gate length of about 1 .mu.m is at most 10 ns, and hence at most 370 ns is required for a sample, and the upper limit of the frequency is 2.7 MHz. Under this condition, a real-time video signal (14.3 MHz to 7.15 MHz) cannot be processed.
TABLE 1 __________________________________________________________________________ STEP PROGRAM __________________________________________________________________________ 1 RA=MA0 RB=MA7 2 RA=MA1 ACC=RA+RB RB=MA6 3 RA=MA3 ACC=RA+RB MA8=ACC RB=MA4 4 RA=MA2 ACC=RA+RB MA9=ACC RB=MA5 5 RA=MA1 ACC=RA+RB MA10=ACC RB=MA6 6 RA=MA2 RC=RA-RB MA11=ACC RB=MA5 RD=MR0 7 RA=MA8 RC=RA-RB RE=RC*RD RB=MA10 RD=MR0 8 RA=MA9 ACC=RA+RB RE=RC*RD MA16=RE RB=MA11 9 RA=MA8 ACC=RA+RB MA17=RE RB=MA10 MA0=ACC 10 RA=MA9 ACC=RA-RB MA21=ACC RB=MA11 11 RA=MA12 ACC=RA-RB MA22=ACC RB=MA14 12 RA=MA13 ACC=RA+RB MA23=ACC RB=MA15 13 RA=MA12 ACC=RA+RB MA24=ACC RB=MA14 14 RA=MA13 ACC=RA-RB MA25=ACC RB=MA15 15 RA=MA20 ACC=RA-RB MA26=ACC RB=MA21 16 RA=MA20 ACC=RA+ RB MA27=ACC RB=MA21 17 RA=MA22 ACC=RA-RB MA0=ACC RB=MA23 18 RA=MA24 RC=RA-RB MA4=ACC RB=MA25 RD=MR3 19 RA=MA26 RC=RA-RB, RE=RC*RD RB=MA17 RD=MR6 20 RC=RA-RB, RE=RC*RD, MA18=RE RD=MR9 21 RC=MA22 RE=RC*RD, MA19=RE RD=MR1 22 RC=MA23 RA=RC*RD, MA20=RE RD=MR2 RB=MA18 23 RC=MA24 ACC=RA-RB, RA=RC*RD RB=MA4 RB=MA18 24 RC=MA25 ACC=RA+RB, RA=RC*RD, MA2=ACC RD=MA5 RB=MA19 25 RC=MA26 ACC=RA-RB, RA=RC*RD, MA6=ACC RB=MA7 RB=MA19 26 RC=MA27 ACC=RA+RB, RA=RC*RD, MA1=ACC RB=MA8 RB=MA20 27 ACC=RA-RB, RA=RC*RD, MA7=ACC RB=MA20 28 ACC=RA+RB MA5=ACC 29 MA3=ACC __________________________________________________________________________
The above technology discussed by the present inventors prior to the filing of this application is subject to the problem that the object of the computing algorithm is placed only on the reduction of the number of additions and multiplications and that the usage of the DSP is not taken into consideration. The algorithm above is irregular and is hence not inherently suitable for high-speed DSP operation.